Development of Reduced Switch 21 Level Asymmetric Inverter without Inversion Circuit for Dynamic Load Conditions

Vijayaraja Loganathan1 , Dhanasekar Ravikumar2 , Ganesh Kumar Srinivasan3 and Vikash Paul4

1.2 Department of Electrical & Electronics Engineering, Sri Sairam Institute of Technology, West Tambaram, Chennai, Tamilnadu, India

3.4Department of Electrical & Electronics Engineering, CEG campus, Anna University, Chennai, Tamilnadu, India

vijayaraja.eee@sairamit.edu.in, dhanasekar@sairamit.edu.in, ganeshkumar@annauniv.edu, vikashrpaul@gmail.com

Abstract: Generating higher voltage steps at the load terminal using asymmetric configuration of DC source with limited switch count is more attracted by the researchers in recent days. Therefore producing higher voltage steps using multilevel inverter (MLI) with minimum part count leads to reduction in cost and size. So here a construction and software validation of a MLI to produce higher voltage level without inversion circuit is performed. The constructed MLI is able to provide 21 voltage steps at the load using 3 DC sources which are having unequal voltage values and 10 switches. The switching circuit is designed to perform the necessary logic pulse generation for the switches in the MLI circuit using nearest level scheme. Further software validation is done using MATLAB/Simulink and the designed MLI is tied to R, Z and induction motor loads and the THD% is observed as 4.73, 4.82 and 4.12 % . Also the inverter achieves a remarkable efficiency of 96.83% for a resistive load of 150Ω and 1000 W. This shows that the proposed MLI lowers THD which results in smoother operation of connected loads, reduced heating, and improved efficiency. The performance of the 21 voltage step MLI is observed and it is presented here. Also a comparison study based on switch count, independent source and THD% is made between the proposed MLI, conventional and recent MLIs. The hardware implementation is carried out using SPARTAN 6, and the results are presented for fixed and variable R and Z loads. Thus the proposed 21-level MLI stands out due to its; simplified topology with reduced component count, high-quality output waveform with low THD, broad applicability across load types, including dynamic motor loads and high efficiency with adherence to industry standards.

Keywords: Asymmetric inverter; modes of operation; multi-level inverter; power electronics; reduced switch component.

1. Introduction

Multi-Level Inverters (MLI) have become a revolution in the world of power electronics for its improved voltage and current waveforms, high power applications and for power quality demanding applications. They also find applications in speed drive control, STATCOMS, HVDC and HVAC transmissions. The advantages of multi-level inverters are used in higher voltage operability, reduced voltage derivatives, reduced voltage harmonic components, fault tolerant operation and increased efficiency. The current trend applications for MLIs are around photovoltaic conversions, electric vehicle technology, wind energy technology etc. MLI consists of various circuit components such as diodes, voltage sources and switches. Based on the construction of the circuit and the voltage sources considered, the inverters are classified as symmetric and asymmetric MLIs and to be specific they are further classified as: series-mode half-bridges, clamp-on diodes and capacitor-to-float converters [1]–[2].

In symmetric MLIs, the DC sources have the same amplitude in their configuration, whereas in asymmetrical inverters the sources have non identical source ratings in their configuration. All these types of conventional type MLIs have a greater number of switches in

Received: October 7th, 2024. Accepted: November 30th, 2024

DOI: 10.15676/ijeei.2024.16.4.6

their design which directed to construct MLI with reduced components. As reduced number of switches is required, asymmetrical MLIs are identified for operation. Due to the reduced switch count, the switching power losses are lowered drastically. Also, another big advantage of asymmetrical configuration is that for the same switch count, higher level can be obtained in asymmetrical configuration compared to symmetrical configuration. Required parameters for the design of a MLI are number of levels to be acquired; count of the switches needed for the required levels, harmonic occupancy in voltage obtained at output, the count of independent DC sources needed to generate the required +levels, switch stress and the standing voltage.

However, for achieving more number of levels, greater quantities of switches are required. So, a solution is needed to have additional levels and to have reduced switching components [3]-[6]. For better performance of the MLI, the harmonic distortion finds a crucial role. The achievement of the MLI can be inferred from the amount of harmonic distortion present at the load current and voltage. The harmonic distortion must be reduced, so that the MLI performance can be improved. For the reduction of harmonic distortion, the PWM techniques engaged in the semiconductor switches plays a central role. This also helps in providing the required switching pattern such that a sinusoidal wave across the load can be achieved. In light of the aforementioned, numerous efforts have been made over the past few years to decrease the switch count; these efforts are covered in [7]–[11]. These works have produced some new topologies and structures with a smaller number, although each has flaws of its own.

Further, MLI configurations shown in [17] and [18] are capable of producing 13 levels at the load using 14 and 13 switches respectively. Where configuration developed in [17] uses capacitor for clamping the voltages and is of floating types but the number of DC sources present in [17] is 2 when compared to 4 in [18]. The presented MLI in [19] and [20] are able to give 17 levels at the load using 7 and 14 power switches. The MLI circuit in [19] and [20] needs extra capacitors, where the numbers of DC sources connected are 2 and 1. In [21], a 21 level inverter is experimented with 20 switches, 8 diode and capacitors each and 1 DC sources. So, in the view of considering the above discussion, to generate higher voltage levels, a new MLI is to be designed which involves minimum quantity of circuit components.

The proposed model is also a new topology structure with reduced switching component and taken into consideration of the shortcomings to produce a much higher level of output. The proposed model is a new topology for 21-level asymmetric MLI with only 10 switches and 3 unequal D.C. sources. The configuration does not possess inversion circuit, there by operability of the circuit is increased for higher range of voltages.

This paper follows through as given in section II describes the model of proposed circuit, the analysis of switch count, level count and the peak voltage followed by section III which provides the working, modes of operation and the switching sequence of the proposed circuit in a detail manner. Section IV is the results of the proposed model from the simulation. Finally in Section V, conclusions are made on the proposed model which gives a higher voltage with reduced switch count and reduced THD.

2. 21-level inverter with switching sequence

A MLI configuration [12] without inversion circuit is shown in Fig. 1. To obtain 21 levels, the proposed circuit consists of 10 switches and 3 voltage sources. Here, all 10 switches are uni-directional in nature as illustrated in Fig. 2, so that identical driver circuit is used for the switches present in the circuit. A basic sinusoidal PWM technique is used generating triggering pulses for the proposed model. The designed MLI circuit is formed with 3 unequal voltage sources which will make an asymmetric configuration. D.C. voltage sources are identified as 40V, 80V and 280V respectively.

A. MLI Design Criteria

For the inverter topology, mathematical equation is derived with the aim of finding the level count obtained from the inverter and switch count and the voltage sources required for the

inverter. Let the voltage sources required be switch count be \(N_{sw}\), level count of the inverter be \(N_{bl}\).

Figure 1. 21 Level Inverter

Figure 2. Switch Configuration

The switch count for the proposed inverter (N_sw) can be calculated as given in Equation 1,

\[N_{sw} = 2^m + 2 \tag{1}\]

The level count \((N_{lvl})\) for the figure 1 can be calculated from Equation2,

\[N_{lvl} = 7 \times m \tag{2}\]

The peak output voltage \((V_{0, max})\) of the inverter is achieved from Equation 3,

\[V_{0, max} = (2^m + 2) \times V_{DC}\] (3)

Now the proposed topology consists of 3 voltage sources (m = 3), so switch count \(N_{sw} = 10\), the level count of the inverter is \(N_{lvl} = 21\). Here the \(V_{DC} = V_1 = 40V\), so the peak output voltage can be given as \(V_{0, max} = 400V\).

where 'm' is the number of DC voltage sources and '\(V_{DC}\)' is the fundamental DC voltage source value.

B. Pulse Generation

The pulses that are to be given to the switches are generated by using four divisions, sine wave signal as reference, comparator for comparing the reference wave and the gain, relational and logic circuit are used for producing the pulses for the switches and driver circuits for the triggering of the switches. These four divisions can be demonstrated as illustrated in Fig. 3.

Figure 3. Various Divisions of Pulse Generation

From the block diagram (Fig 3), a sine wave is taken as reference and the amplitude of the reference wave is taken as 11V. Its chosen based on the positive level and zero level needed for the MLI. This reference wave is given as the input to the comparator. The output of the comparator obtained is directed to relational and logic circuit block. Here relational operators

are used to compare the levels that are to be selected. For each level a pair of relational operators and an AND gate is used for the generation of the pulses. This output is sent to a driver circuit which consists of a sum block and multiport switch block. The sum block collects all the pulses that is to be selected for each switching sequence. The switching order in which the switches are to be switched on is provided by the multiport block. The switching sequence of the appropriate level is coded into the multiport block as its input for each level. Right now the four divisions are implemented for each level coded with their respective switching sequence and then given to the IGBT switches used in the proposed configuration.

C. Modes of operation

The inverter is designed to work in 21 modes of operation to construct an alternating waveform. For understanding purpose; few modes are explained in Fig. 3. Device status for each mode of operation is given below,

Mode-1:S2, S3, S5, S7, S10 devices are 'ON' to generate 400V Mode-2: S2, S3, S6, S7, S10 devices are 'ON' to generate 360V Mode-3: S2, S5, S7, S8, S10 devices are 'ON' to generate 320V Mode-4: S2, S3, S4, S5, S10 devices are 'ON' to generate 280V Mode-5:S2, S3, S4, S6, S10 devices are 'ON' to generate 240V Mode-6:S1, S3, S6, S7, S9 devices are 'ON' to generate 200V Mode-7:S2, S4, S6, S8, S10 devices are 'ON' to generate 160V Mode-8:S3, S5, S7, S9, S10 devices are 'ON' to generate 120V Mode-9:S9, S6, S7, S9, S10 devices are 'ON' to generate 80V Mode-10:S5, S7, S8, S9, S10 devices are 'ON' to generate 40V Mode-11:S6, S7, S8, S9, S10 devices are 'ON' to generate 0V Mode-12:S3, S4, S6, S9, S10 devices are 'ON' to generate -40V Mode-13:S4, S5, S8, S9, S10 devices are 'ON' to generate -80V Mode-14:S4, S6, S8, S9, S10 devices are 'ON' to generate -120V Mode-15:S1, S3, S5, S7, S9 devices are 'ON' to generate -160V Mode-16:S1, S3, S6, S7, S9 devices are 'ON' to generate -200V Mode-17:S1, S5, S7, S8, S9 devices are 'ON' to generate -240V Mode-18:S1, S6, S7, S8, S9 devices are 'ON' to generate -280V Mode-19:S1, S3, S4, S6, S9 devices are 'ON' to generate -320V Mode-20:S1, S4, S5, S8, S9 devices are 'ON' to generate -360V Mode-21:S1, S4, S6, S8, S9 devices are 'ON' to generate -400V

From the modes of operation, the Fig. 4 is drawn to demonstrate the switching states of the inverter circuit.

Figure 4. Modes of Operation for 21 level inverters

3. Simulation and Results

The Fig 5a to 5c shows the PWM pulse generation waveforms to the inverter circuit. In Fig. 5d, the simulated result of the proposed inverter simulated in MATLAB/SIMULINK with resistive load of 150Ω is shown.THD of the inverter's voltage wave shape is 4.73% and it is inside the scope of guidelines as given in IEEE 519. The proposed circuit constructs a crest-tocrest voltage of ±400V as illustrated from Fig. 4.

Figure 5(a). Input pulses generated for switches S1 to S4

X axis - 1 cm = 0.01 seconds Y axis - 1 cm = 1 volt

Figure 5(b). Input pulses generated for switches S₅ to S₈

X axis - 1 cm = 0.01 seconds Y axis - 1 cm = 1 volt

Figure 5(c). Input pulses generated for switches \(S_9\) and \(S_{10}\)

Figure 5 (d). Results of the circuit tied with R Load of 21-level inverter (Voltage THD)

Further, the proposed circuit is simulated for a R-L load, with R=150 \(\Omega\), L = 0.477 H. The output voltage for the RL load for the proposed inverter is displayed in Fig. 5e and the THD for the presented inverter's output voltage is 4.82% and current THD is 2.78% as shown in Fig. 5f.

Figure 5(e). Results of the circuit tied with RL Load of 21-level inverter (Voltage THD)

Figure 5(f). Results of the MLI circuit tied with RL load (Current THD)

Calculation of Power loss for proposed Multi level Inverter

The primary cause of the conduction loss (Pcl) in power semiconductor switches are dues to its internal resistance Rin during their on-state and Pcl can be computed using equation 4,

\[P_{cl} = \sum_{j=1}^{14} R_{in} \, l_{out}^{2} \tag{4}\]

Turn-on power loss (Pswl,ON) and turn-off power loss (Pswl,OFF) are the terms which describes the switching losses that results from the overlap of current and voltage across the switches during the transition of switching states and it is computed from 5 to 8.

\[P_{\text{swl,ON}} = \int_0^{t_{on}} v(t)i(t)dt = fs\left(\frac{-Vb(t-t_{on})}{t_{on}}\right)\left(\frac{I_{out}}{t_{on}}t\right)dt = \frac{1}{6}fs\ V_{bl}I_{out}t_{on}\] \[= \frac{-Vb(t-t_{on})}{t_{on}}\left(\frac{I_{out}}{t_{on}}t\right)dt = \frac{1}{6}fs\ V_{bl}I_{out}t_{on}\] (5)

\[P_{\text{swl,OFF}} = f s \int_{0}^{t_{off}} v(t) i(t) dt = f s(\frac{v_{off}}{t_{off}}) \left(\frac{t_{out}}{t_{off}}t\right) dt\] (6)

\[P_{swl} = P_{swl,ON} + P_{swl,OFF} \tag{7}\]

\[P_{swl} = \sum_{j=1}^{14} fsj * Vbj * Iout * (ton + toff)\] (8)

The total power losses \((P_{pl})\) and the efficiency are obtained as

\[P_{pl} = P_{cl} + P_{swl}\] \[\eta = \frac{P_o}{P_o + P_{pl}}\] \[[(P_o) \text{ is obtained from V}_{rms}*I_{rms}]\] \[(9)\]

From the above equations the efficiency of the proposed 21 level MLI is obtained as 96.83% for 150 \(\Omega\), 1000 W load. The proposed circuit is also simulated for induction motor load with specification as provided in Table 1 and Fig. 5g shows the main winding current of the induction motor tied with 21-level inverter.

Table 1. Specification of IM load

Figure 5(g). Results of the 21-level circuit tied with induction motor load (main winding current)

Figure 5(h). Results of the MLI circuit tied with induction motor load (Speed)

Figure 5(i). Results of the inverter circuit tied with induction motor load (Load torque)

When the circuit is tied with an induction motor, the motor settles at a speed of 1451 rpm, due to a load torque of 2 Nm, as presented in Fig. 5h and 5i respectively. Now the THD of the circuit after connecting it with a motor load is 4.12% that can be shown in Fig. 5j.

Figure 5(j). Results of the circuit tied with induction motor Load of 21-level inverter (Voltage THD)

4. Comparative Study

Multiple structures for the MLI have been presented to reduce the switch count. The structure realized in [13] is a 51-level symmetric structure consisting of 9 level structures in cascade with an H-bridge circuit. This structure has 25 independent sources, each having a magnitude of 1 Volt, along with 46 power switches. Due to the symmetrical structure, achieved output voltage is less, but the circuit has a low THD value of 1.95%. The proposed MLI in [14] produced 31-levels are obtained using asymmetric configuration. This configuration consists of ten power switches and six independent sources. The negative levels obtained using an Hbridge and the THD value obtained for reactive load is 3.18%. By using the basic principle of CHB inverters, a new cascaded topology is realized in [15]. The basic unit is made of 3 independent sources and 5 power switches. This basic unit is cascaded with H-bridge to obtain multiple levels. Using one base unit 9 levels are achieved with a THD value of 18.8%. Cascading two basic units, a 15 level inverter is achieved with a THD value of 14.16%. By cascading the basic unit the output voltage levels that are obtained are 27, 33, 39 and their respective THD values are 12.07, 11.85 and 11.33% respectively. In [16] 57-level inverter is realized which is constructed using 9 cascaded structures with an H-bridge. The basic unit consists of 3 independent sources and 6 power switches. The symmetric configuration consists of a total switch count of 51 and 28 independent sources to obtain the 57-level output. Also, the same levels of output can be obtained in an asymmetrical configuration with only two basic units where the switch count is 18 and the number of independent sources is seven.

Figure 6(a). Comparative study for switch count

Figure 6(b). Comparative study for independent sources

Figure 6(c). Comparative study for THD%

Figure 6(d). Comparative study for efficiency%

Also analysis is made for the efficiency of the proposed inverter with other MLI's for the same power and it is calculated as 96.83%. Comparative plot on switch count, independent source, THD% and efficiency for the reference papers [13] – [16] with respective to proposed topology is exhibited in Fig. 6(a), 6(b), 6(c), and 6(d) respectively. A 21-level configuration of MLI which make use of minimal switch count has been designed and the proposed circuit can achieve the maximum voltage with minimum number of switches with a low THD, thereby reducing the cost and size. Comparison between the proposed circuit with traditional inverters such as: cascaded H-Bridge, diode clamped and flying capacitor inverters are demonstrated from Fig. 7 (a) to Fig 7 (e).

Figure 7(a). Number of Switches

Figure 7(b). Number of driver circuits

Figure 7(c). Number of voltage sources

5. Real time validation

From the comparative study it is proved that design of 21-level inverter discussed here utilizes minimum number of components compared to the other MLI designs. Therefore the hardware implementation of the 21-level multilevel inverter is carried out with the components as given in Table 2. It involves the various parts like the power supply, inverter circuit, FPGA controller unit and the driver circuit. Using VHDL coding, program is written and dumped into the FPGA SPARTAN 6 controller unit and using driver circuit the pulses will be given to the IGBT's that are present in the 21-level MLI. Finally, the performance of the inverter is studied by connecting it to fixed R and Z load, variable R and Z load conditions.

The magnitudes of the DC sources are selected as: \(V_1 = 40 \text{ V}\), \(V_2 = 80 \text{ V}\), \(V_3 = 280 \text{ V}\) for the real time implementation. For validation of the proposed inverter, a prototype of multilevel inverter circuit is developed and tested as shown in Fig. 8.

A. 21-Level MLI with Resistive Load

The hardware setup is shown in Fig. 8 is connected to a resistive load of R=100 \(\Omega\) and the output voltage, current is viewed from DSO. Fig. 9 shows both the current and voltage waveform at the output. This depicts that, both the voltage and current waveform are in phase with each other. The output voltage has the maximum value of \(\pm 400\) V and the output current value of 0.4 A.

Figure 8. Hardware implementation of 21-level MLI for resistive load

To check the stability of the inverter, it is tied to variable R load conditions (ie., the resistance value is being varied from a low value to certain high value) and the performance of the inverter is observed satisfactory. Fig. 10 depicts the output voltage and current waveform for variable R load conditions. The current waveform (2) clearly shows the variation of the current while the resistance is being varied. The current value is larger while the resistance value is lowered.

Figure 9. 21-level MLI output voltage and current waveform for resistive load

Figure 10. 21-level MLI output voltage and current waveform for variable R load

B. 21-Level MLI with Reactive Load

The hardware setup for the 21-level MLI for reactive load is shown in Fig. 11. The resistance value is kept at R=100 Ω and inductance L=120 mH.

Figure 11. Hardware implementation of 21-level MLI for RL load

Fig. 12 depicts the output voltage waveform and current waveform and the load values are observed as ±400 V and 0.3 A respectively. From the load waveform, it is seen that the current waveform clearly indicates that in inductive load condition the current lags the voltage. The

comparison for the THD at the output voltage for both the simulation and hardware results are represented in the Table 3 and it is seen that the observed values are as per the IEEE standard.

Table 3. THD comparison of 21-level MLI

Figure 12. 21-level MLI output voltage and current waveform for RL load

The inductance value is maintained constant at L=120 mH but the resistance value is being varied. Fig. 13 depicts the output voltage waveform and current waveform for variable RL load. The current waveform in Fig. 13 clearly shows the variation of the current while the resistance is being varied. The current is larger while the resistance value is low and decreases furthermore while the resistance value is lowered.

Figure 13. 21-level MLI output voltage and current waveform for variable RL load

6. Conclusion

As the inverter plays a vital role in renewable energy integration, here a 21 level inverter is designed using 3 DC asymmetric voltage sources, 10 power switches. A thorough analysis is made to design the 21-level MLI. Further, the proposed circuit is drive through fundamental frequency pulse width modulation and it is modeled in MATLAB/Simulink environment and the simulation results are presented. The design parameters are compared with conventional MLI, recent MLIs and it is inferred that the proposed 21-level MLI performs better compared than the other MLI designs. In continuation with this, the hardware implementation is carried and satisfactory results have been obtained. The simulation results showing THD values of 4.73% for resistive loads and 4.82% for RL loads. Hardware implementation results closely align with these values (4.86% and 4.93%, respectively), validating the design and meeting IEEE 519 standards. Also while connected to an induction motor load, the MLI provided efficient performance with low THD (4.12%). The motor achieved stable operation at 1451 RPM under a load torque of 2 Nm, confirming the inverter's suitability for motor drive applications. The hardware implementation further validates the design, demonstrating excellent agreement between simulation and real-time results. Stability and reliability are confirmed under both fixed and variable load conditions. The presented work can be extended to integration of renewable energy sources such as solar PV or fuel cells. Thus the proposed 21-level MLI achieves high-quality performance with reduced hardware requirements, making it a promising solution for modern power electronics applications.

7. Acknowledgment

Authors acknowledge the Department of Electrical and Electronics Engineering at Anna University and the RUSA 2.0 (PO 2) project for their financial support.

8. References

• [1]. K. K. Gupta, A. Ranjan, P. Bhatnagar, L. K. Sahu, and S. Jain, ''Multilevel inverter topologies with reduced device count: A review,'' IEEE Trans. Power Electron., vol. 31, no. 1, pp. 135–151, Jan. 2016.
• [2]. G. K. Srinivasan, M. Rivera, V. Loganathan, D. Ravikumar, and B. Mohan, "Trends and Challenges in Multi-Level Inverter with Reduced Switches," Electronics, vol. 10, no. 4, p. 368, Feb. 2021.
• [3]. V. L, G. K. S, M. Rivera and E. Babaei, "Performance Enhancement of Reduced Component Multilevel Inverter with Optimal Placement of Level Shifter," in IEEE Latin America Transactions, vol. 22, no. 6, pp. 502-511, June 2024, doi: 10.1109/TLA.2024.10534310.
• [4]. Z. E. Abdulhamed, A. H. Esuri and N. A. Abodhir, "New Topology Of Asymmetrical Nine-Level Cascaded Hybrid Bridge Multilevel Inverter," 2021 IEEE 1st International Maghreb Meeting of the Conference on Sciences and Techniques of Automatic Control and Computer Engineering MI-STA, 2021, pp. 430-434, doi: 10.1109/MI-STA52233.2021.9464511.
• [5]. Sheikh Tanzim Meraj, Nor Zaihar Yahaya, Kamrul Hasan, Ammar Masaoud,A hybrid Ttype (HT-type) multilevel inverter with reduced components, Ain Shams Engineering Journal,Volume 12, Issue 2,2021,Pages 1959-1971,ISSN 2090-4479.
• [6]. P. Ponnusamy et al., "A New Multilevel Inverter Topology With Reduced Power Components for Domestic Solar PV Applications," in IEEE Access, vol. 8, pp. 187483- 187497, 2020, doi: 10.1109/ACCESS.2020.3030721.
• [7]. L. Vijayaraja and S. Ganesh Kumar, "Analysis and Development of 53-Level Asymmetric Multilevel Inverter with Reduced Component for Fixed and Variable Loads", in Electric Power Components and Systems, vol. 50, no. 16-17, pp. 931-950, 2022.

• [8]. M. D. Siddique, S. Mekhilef, N. M. Shah, A. Sarwar, A. Iqbal and M. A. Memon, "A New Multilevel Inverter Topology With Reduce Switch Count," in IEEE Access, vol. 7, pp. 58584-58594, 2019.
• [9]. M. D. Siddique, S. Mekhilef, N. M. Shah and M. A. Memon, "Optimal Design of a New Cascaded Multilevel Inverter Topology With Reduced Switch Count," in IEEE Access, vol. 7, pp. 24498-24510, 2019, doi: 10.1109/ACCESS.2019.2890872.
• [10]. E. Samadaei, S. A. Gholamian, A. Sheikholeslami and J. Adabi, "An Envelope Type (E-Type) Module: Asymmetric Multilevel Inverters With Reduced Components," in IEEE Transactions on Industrial Electronics, vol. 63, no. 11, pp. 7148-7156, Nov. 2016, doi: 10.1109/TIE.2016.2520913.
• [11]. V. Loganathan, G. K. Srinivasan, and M. Rivera, "Realization of 485 Level Inverter Using Tri-State Architecture for Renewable Energy Systems," Energies, vol. 13, no. 24, p. 6627, Dec. 2020.
• [12]. S. R. Khasim, D. C, S. Padmanaban, J. B. Holm-Nielsen and M. Mitolo, "A Novel Asymmetrical 21-Level Inverter for Solar PV Energy System With Reduced Switch Count," in IEEE Access, vol. 9, pp. 11761-11775, 2021, doi: 10.1109/ACCESS.2021.3051039.
• [13]. B. Ganesh et al., "Implementation of Twenty seven level and Fifty one level Inverter using constant voltage sources," 2019 IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies (CHILECON), 2019, pp. 1-4, doi: 10.1109/CHILECON47746.2019.8987978.
• [14]. G. Raman, A. Imthiyas, M. D. Raja, L. Vijayaraja and S. G. Kumar, "Design of 31-level Asymmetric Inverter with Optimal Number of Switches," 2019 IEEE International Conference on Intelligent Techniques in Control, Optimization and Signal Processing (INCOS), 2019, pp. 1-3, doi: 10.1109/INCOS45849.2019.8951354.
• [15]. S. Ponkumar, S. M. Rivera, F. Kamroon and S. G. Kumar, "Realization of cascaded multilevel inverter," 2017 CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies (CHILECON), 2017, pp. 1-7, doi: 10.1109/CHILECON.2017.8229701.
• [16]. L. Vijayaraja, V. Nandhinipriya, R. Dhanasekar, S. G. Kumar and M. Rivera, "Simulation and Experimentation of 57-Level Inverter," 2021 IEEE International Conference on Automation/XXIV Congress of the Chilean Association of Automatic Control (ICA-ACCA), 2021, pp. 1-8, doi: 10.1109/ICAACCA51523.2021.9465284.
• [17]. E. Samadaei, M. Kaviani and K. Bertilsson, "A 13-Levels Module (K-Type) With Two DC Sources for Multilevel Inverters," in IEEE Transactions on Industrial Electronics, vol. 66, no. 7, pp. 5186-5196, July 2019, doi: 10.1109/TIE.2018.2868325.
• [18]. M. D. Siddique, A. Iqbal, M. A. Memon and S. Mekhilef, "A New Configurable Topology for Multilevel Inverter With Reduced Switching Components," in IEEE Access, vol. 8, pp. 188726-188741, 2020, doi: 10.1109/ACCESS.2020.3030951.
• [19]. C. Dhanamjayulu, D. Prasad, S. Padmanaban, P. K. Maroti, J. B. Holm-Nielsen and F. Blaabjerg, "Design and Implementation of Seventeen Level Inverter With Reduced Components," in IEEE Access, vol. 9, pp. 16746-16760, 2021, doi: 10.1109/ACCESS.2021.3054001.
• [20]. K. Singh and R. K. Mandal, "A Novel 17-Level Reduced Component Single DC Switched-Capacitor-Based Inverter With Reduced Input Spike Current," in IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 10, no. 5, pp. 6045-6056, Oct. 2022, doi: 10.1109/JESTPE.2022.3166222.
• [21]. M. F. Talooki, M. Rezanejad, R. Khosravi and E. Samadaei, "A Novel High Step-Up Switched-Capacitor Multilevel Inverter With Self-Voltage Balancing," in IEEE Transactions on Power Electronics, vol. 36, no. 4, pp. 4352-4359, April 2021, doi: 10.1109/TPEL.2020.3019223.

Vijayaraja Loganathan (Member in IEEE) was born on May 30, 1983 and in 2023 from Anna University in Chennai, India, where he earned his Ph.D. He is currently employed by Sri Sairam Institute of Technology in Chennai, India, as an Associate Professor. Electric vehicles, power converter and inverter designs, renewable energy sources are among his research interests. More than 60 of his research papers have been published in academic journals, conferences held abroad, and technical book series. Also, he has more than 5 patents and 2 patent grants in his area of study.

Dhanasekar Ravikumar (Senior Member in IEEE) is currently working as an Associate Professor in the Department of Electrical and Electronics Engineering at Sri Sairam Institute of Technology, Chennai, India. He has served as a reviewer for international journals, including IEEE Latin America Transactions, Electric Power Components and Systems, Journal of Dynamic Systems, Measurement and Control, and Scientific Reports. He graduated with a degree in Electrical and Electronics Engineering from RVS College of Engineering & Technology, Tamilnadu, India, in 2004, earned his

Master's in Power Electronics & Drives from Mepco Schlenk Engineering College, Tamilnadu, India, in 2006, and completed his PhD at CEG, Anna University, Chennai, Tamilnadu, India.

Ganesh Kumar Srinivasan (Member in IEEE) is presently working as Professor in the Department of EEE, College of Engineering Guindy, Anna University, Chennai, India. He actively involved in the field of multilevel inverters and control of power converters. He has published 29 journals, 32 conference papers and 3 patents. He have completed two research projects with Rs 27 Lakhs and presently doing two projects of worth Rs 3 Crores.

Vikash Paul was born on Nov 04, 1997 and in 2015 from RMK College of Engineering & Technology, Chennai, India, where he earned his Bachelor's in Electrical & Electronics and in 2022 from College of Engineering, Anna University, Chennai, India, where he earned his Masters in Control & Instrumentation Engineering.